Method and apparatus for interleaving multiple frames of data

ABSTRACT

A method and apparatus for interleaving multiple frames of data as disclosed provide for an extremely streamlined approach to achieving both methods of interleaving as defined in the IS-2000 standard while meeting the complex requirement of frame puncturing. Output addressing is directly driven by a PN index or a counter locked to the reverse link timing, it is a simple manner of range selection to achieve all possible configurations required in the IS-2000 standard. Puncturing of sub-20 ms frames is also easily accomplished by using a single contiguous memory and interleaver engine that resides in the input side of the interleaver memory.

TECHNICAL FIELD

[0001] This invention relates in general to the field of radiocommunications and more specifically to a method and apparatus forinterleaving multiple frames of data.

BACKGROUND

[0002] In modern Direct Sequence Spread Spectrum (DSSS) modulators, datais convolutionally or turbo encoded, punctured, and interleaved prior totransmission. The Telecommunication Industry Association (TIA) IS-2000standard outlines two interleaving requirements, one for backwardcompatibility with previous DSSS standards, and a second for newlyintroduced data rates and channel structures. The IS-2000 standard alsorequires puncturing of 20 millisecond (ms) frames with 5 ms or 10 msframes. “Puncturing” in the current context means replacing some portionof a 20 ms frame with a shorter length (5 ms or 10 ms) frame. Theportion may be any one of the four possible quadrants of a 20 ms frame(5 ms puncturing), or one of either the first or the second halves of a20 ms frame (10 ms puncturing). In either case, more than oneinterleaver configuration must be employed (one for the original 20 msframe and one for the punctured frame). The interleaving mechanism forIS-2000 is given in the standard as a read-address generator, implyingthe function would be implemented at the output or “read” side of theinterleaver memory. Doing this would cause the output address controlcircuitry to be unnecessarily complex since one interleaving engine witha dedicated memory per data channel would be necessary to accomplish thepuncturing.

[0003] IS95 interleaver designs include a two-stage approach forinterleaving data. First a write function is used to place data inmemory, then a specialized read function is used to access the data fortransmission. A traditional modulator 100 configuration is shown inFIG. 1. A write address generator 102 is used to place data in memory106, while a read address generator 104 is used to access data frommemory 106.

[0004] The modulator architecture shown in FIG. 1 may work for theIS-2000 standard, but substantial control circuitry will be required toorchestrate the puncturing of sub-20 ms frames on the output side of thememory. The IS-2000 complexity is increased because multiple interleaverengines are needed to build individual channels when puncturing of 20msec frames occurs. A need thus exists in the art for a method andapparatus that can handle transmission data in the modulator and thatcan support a variety of interleaver structures and perform efficientpuncturing of frames.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The features of the present invention, which are believed to benovel, are set forth with particularity in the appended claims. Theinvention, may best be understood by reference to the followingdescription, taken in conjunction with the accompanying drawings, in theseveral figures of which like reference numerals identify like elements,and in which:

[0006]FIG. 1 shows a prior art modulator.

[0007]FIGS. 2A and 2B highlight the interleaving method used in theIS-2000 standard for IS95A/B interleaving.

[0008]FIG. 3 shows an IS-95 interleaving in accordance with theinvention.

[0009]FIG. 4 shows the mapping from ‘input-based interleaving’ to‘output-based interleaving’ in accordance with the invention.

[0010]FIG. 5 shows an IS-2000 bit-exact interleaving implementation inaccordance with the invention.

[0011]FIG. 6 shows illustrates a memory addressing technique inaccordance with the invention.

[0012]FIG. 7 shows a modulator in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0013] While the specification concludes with claims defining thefeatures of the invention that are regarded as novel, it is believedthat the invention will be better understood from a consideration of thefollowing description in conjunction with the drawing figures, in whichlike reference numerals are carried forward.

[0014] The present invention provides for a seamless solution to thepunctured frame requirement of the IS-2000 standard while providing fora simplified hardware flow for interleaving. The invention also providesfor a flexible method for allocating multiple reverse link channels,each of programmable size within a single interleaver memory. A PN indexin the addressing of the interleaver memory for the transfer of data tothe spreading/filtering unit is utilized which allows for leveraging thePN index and thereby simplifying the overall design.

[0015] All interleaving is done on the input side of the memory by“inverting” the process in the case of IS-2000 interleaving, andcombining the output portion within the input portion, in the case ofthe IS-95 standard interleaving. IS-95 interleaving is defined by twostages: write by column, and read by row. With the current invention,both functions are performed at the same time, i.e. before being writtento the interleaver memory. With inverse interleaving, the entire 20 msframe is built in the first pass, then portions of the frame aredirectly replaced by simply changing the write-address offset andover-writing the appropriate area of interleaver memory using adifferent set of interleaving parameters. For example, in the case ofpuncturing a 5 ms frame into a 20 ms frame, the 20 ms frame data isfirst interleaved and deposited in memory, after which the 5 ms frame isinterleaved over the appropriate quadrant within the 20 ms frame withinthe memory. Thus, the entire buffer may be read out of the interleavermemory sequentially.

[0016] Simplified Interleaving

[0017] The interleaving function is simplified in accordance with theinvention by consolidating the interleaving at the input side of theinterleaver memory as will be discussed below. By doing so, data readfrom the interleaver memory may be accessed sequentially. The prior artof the IS-2000 standard indicates two interleaver structures in whichinterleaving is done when reading from the interleaver memory. Both ofthese interleaver structures need to be inverted to perform the completeinterleaving function at the input side of the memory. The firstinterleaver described in the standard is required for backwardcompatibility with IS-95 systems, while the second meets therequirements of the IS-2000 standard. The following sections offer adetailed description of the inverse interleaving and output addressing.

[0018] IS-95 interleaver (and RC1 & RC2 of the IS-2000 standard)

[0019] As shown in FIGS. 2A and 2B, the prior art interleaving methoddefined in the IS-2000 standard indicates writing data into a32×18-memory array by column and then reading out from the array by row.In the standard, the read-row order is determined by swapping certainbits in a 5-bit sequential address as follows:

[0020] (1). For full rate (9600 or 14400 bps), there is notransformation. The address is applied sequentially: A₄A₃A₂A₁A₀

[0021] (2). For ½ rate (4800 or 7200 bps): A₄A₃A₂A₀A₁

[0022] (3). For ¼ rate (2400 or 3600 bps): A₄A₃A₁A₀A₂

[0023] (4). For ⅛ rate (1200 or 1800 bps): A₄A₂A₁A₀A₃

[0024] (5). For Access Channel: A₀A₁A₂A₃A₄

[0025] The objective of the interleaving is to accept input datasequentially in time, place it into the position in memory from which itshould be read using a sequential addressing scheme. In other words,both write and read functions of the interleaver are merged into onefunction. FIG. 2A shows the mapping process of input data (by row) toits final read-ordered position in memory, if the memory were configuredthe way the algorithm is defined in the standard (32×18). The firstcolumn is the row read order given by the standard. The second column isthe input order of the data, and the third is the new write addressrequired to avoid read-row randomization (i.e., when reading from theinterleaver memory).

[0026] For example, in the 2400/3600 bps example, looking at the “DataInput Order” column, it is shown that the 0^(th) input is read out firstbased on the standard algorithm (generic read order column). Therefore,it should be stored in New Write Address=“0”. The 1^(st) input is readout 3^(rd) so goes in New Write Address=“2”. The 2^(nd) input is readout second so belongs in New Write Address=‘1’, and so forth.

[0027] Since the original algorithm states that data is written in32-bit columns from top to bottom, as shown in FIG. 2B in table 202, andread out by interleaved row, it can be shown that the mapping process inFIG. 2A succeeds in re-ordering the rows so they can be read outsequentially yet still be interleaved properly. A re-mapping function isapplied to a sequential input address generator in order to select theappropriate bit for each 32-bit input column.

[0028] Having re-mapped the position of the input data within eachcolumn denoted in table 202 as TN, we now have a 32×18 bit matrix ofdata. It is desirable to provide one six-bit value at each address inmemory so as to simplify the retrieval of data by the output addressingmechanism (since six symbols are used every 256 PN chips). In order toaccomplish this, each 18-bit word is remapped into three six-bit words,each at its own location in memory.

[0029] It is shown in table 202 that each 32-bit input in the originalmatrix must be further mapped into the format shown in table 204. Sincethe input data has already been mapped into read order, we now only haveto determine the address location in memory that each value must beplaced based on where it appears in the 32×18 matrix.

[0030] Each 18-bit word needs to be re-positioned into three six-bitwords, each at its own location address. Inspection of the two matricesreveals the following relationship:

IfTN=0˜5, A _(n) =A _(or)*3;

IfTN=6˜11, A _(n) =[A _(or)*3]+1;

IfTN=12˜17, A _(n) =[A _(or)*3]+2;  (Equation 1)

[0031] This observation means the remapped rows of FIG. 2A are furthermapped as shown in equation 1 above. The implementation of the IS-95interleaver shown in FIG. 3, includes a modulo 6 counter which indexesthrough the groups of six 32-bit columns. It also includes amultiply-by-3 (shift & add) block, and a modulo 3 result which isincremented after each 32×6 group has completed, which satisfies theoffset shown in equation 1 above.

[0032] IS-2000 Interleaver (and RC3˜6 of IS-2000)

[0033] The IS-2000 standard states that “the symbols input to theinterleaver are written sequentially at addresses 0, to the block size(N) minus 1. Interleaved symbols are read out in a permutated order withthe i-th symbol being read from address A_(i), as follows:$\begin{matrix}{A_{i} = {{2^{m}\left( {i{mod}J} \right)} + {{BRO}_{m}\left( \left\lfloor \frac{i}{J} \right\rfloor \right)}}} & \left( {{Equation}\quad 2} \right)\end{matrix}$

[0034] where i=0 to N−1, └x┘ indicates the largest integer less than orequal to x, and BRO_(m)(y) indicates the bit-reversed m-bit value of y.

[0035] In FIG. 4, it is shown how equation 2 works. The left column ofFIG. 4, shows the linearly ordered input bits to the interleaver and theright column shows the linearly ordered output bits. FIG. 4 illustrateshow linearly ordered bits that are received are store in such a way thatthey can be read linearly. FIG. 4 also shows that input bit addressescan be grouped by bunches of 2^(m) consecutive values and that outputbit addresses will receive their inputs from groups of addresses in asequence that repeats every J bits, hence modulo J. FIG. 4 however doesnot indicate which address inside a group is actually sent to the outputcolumn. This is the tricky part of the algorithm where the Bit Reversalcomes into play.

[0036] Look at i within sets of J values, i.e. we apply an integerdivision of i by J; there exist two unique integers k and p such that:

i=kJ +p with 0≦p≦J−1 and k≧0  (Equation 3)

[0037] Substituting Equation 3 into the first part of Equation 2 resultsin:$A_{i} = {{2^{m}\left( {\left( {{kJ} + p} \right)\quad {{mod}J}} \right)} + {{BRO}_{m}\left( \left\lfloor \frac{i}{J} \right\rfloor \right)}}$

$\begin{matrix}{A_{i} = {\left( {2^{m} \times p} \right) + {{BRO}_{m}\left( \left\lfloor \frac{i}{J} \right\rfloor \right)}}} & \left( {{Equation}\quad 4} \right)\end{matrix}$

[0038] By construction of the BRO_(m) function, we have:

0≦BRO_(m)(y)≦2^(m)−1  (Equation 5)

[0039] since BRO_(m) is an m-bit number. Combining Equations 4 and 5 andkeeping in mind that p is positive, leads to the conclusion that p isthe quotient of the integer (Euclidean) division of A_(i) by 2^(m) andthat BRO_(m)(└i/J┘) is the remainder. We may already assert than anincoming bit in the A_(i)-th position will be read in the i-th positionsuch that:

i=kJ+p with p=└A _(i)/2^(m)┘  (Equation 6)

[0040] but we do not know how to process k yet.

[0041] Substituting the value of i in Equation 3, into Equation 4 leadsto: $\begin{matrix}{A_{i} = {\left( {2^{m} \times p} \right) + {{BRO}_{m}\left( \left\lfloor \frac{\left( {{kJ} + p} \right)}{J} \right\rfloor \right)}}} & \left( {{Equation}\quad 7} \right)\end{matrix}$

[0042] The definition of k and p of Equation 3 implies that:$\begin{matrix}{\left\lfloor \frac{\left( {{kJ} + p} \right)}{J} \right\rfloor = k} & \left( {{Equation}\quad 8} \right)\end{matrix}$

[0043] From Equations 7 and 8 we get:

A _(i=)(2^(m) ×p)+BRO_(m)(k)  (Equation 9)

[0044] Now, let q be the remainder of the division of A_(i) by 2^(m):

q=A _(i) mod 2^(m).  (Equation 10)

[0045] It has been shown that: $\begin{matrix}{q = {{{BRO}_{m}\left( \left\lfloor \frac{i}{J} \right\rfloor \right)} = {{BRO}_{m}(k)}}} & \left( {{Equation}\quad 11} \right)\end{matrix}$

[0046] The Bit Reversal function has the obvious property that appliedtwice in a row it is equivalent to zero; hence:

BRO_(m)(q)=BRO_(m)[BRO_(m)(k)]=k  (Equation 12)

[0047] We have now come to the final conclusion, that the A_(i)-th inputbit goes to the i-th address of the output table such that:$\begin{matrix}{i = {{{kJ} + {p\quad {with}\quad p}} = {{\left\lfloor \frac{A_{i}}{2^{m}} \right\rfloor \quad {and}\quad k} = {{BRO}_{m}\left( {A_{i}{{mod}2}^{m}} \right)}}}} & \left( {{Equation}\quad 13} \right)\end{matrix}$

[0048] It is worth mentioning that the J value is chosen in the IS-2000standard to be of the form J=3×2^(n), where n is an integer. This makesthe multiplication by J relatively easy to achieve.

[0049] In FIG. 5, there is shown the hardware implementation of theinverse interleaver of IS-2000. The write address I, is given as:

I=kJ+P

[0050] where: J can be defined as 3*2^(n) or 9*2^(n) (i.e., asdetermined in tables 2.1.3.1.7-1 of the IS-2000 standard, J can bedecomposed in this manner); P=A_(i)/2^(m) and A_(i) is the requestedaddress; k=BROm (A_(i) mod 2^(m)); BROm(y)=bit-reversed m−LSBs of y. Theassignable parameters are: INTL_M which is used for m; INTL_L is used asthe 3 or 9 multiplier in J above; and INTL_N is used for n.

[0051] Use of offset addressing of a single contiguous interleavermemory provides the flexibility to engage different numbers of channelswhile easily configuring them for different rates. This flexibilityallows the most efficient use of data path bandwidth since the memorymay be used for multiple channels of varying data rates, or it may beconsumed by a single high-data-rate channel. Additional flexibility canbe leveraged since both input and output address offsets are appliedallowing any channel to be assigned to any region within the interleavermemory. This provides for a simplified yet maximally flexible method forallocating multiple reverse link channels, each of programmable sizewithin a single interleaver memory.

[0052] In the present invention, utilization of reverse link timingreference in the addressing of the interleaver memory for the transferof data to the spreading/filtering unit. Output data is ultimately Walshcovered (RC3˜6) or Walsh modulated (RC1˜2) and PN-spread prior totransmission by a Walsh function block and PN sequence blockrespectively. An advantage can be gained if a simple counter tied toreverse link timing can be leveraged to address the interleaver memory.

[0053] Typical modulator front-ends require the interleaver memory to betightly coupled to the interleaving function. For example, the IS-95A/Bstandards imply a two-stage interleaving process (write by row, read bycolumn) that complicates the option of leveraging the counter mentionedabove for output addressing. In addition, due to the punctured framerequirement of the IS-2000 standard, typical architectures will not beable to take advantage of the counter without first applying complicatedmanipulations to adjust for punctured frames.

[0054]FIG. 6 illustrates the method of output addressing of the memoryin accordance with one aspect of the invention. Utilization of a countertied to reverse link timing is possible because modulation data durationis given in terms of a finite number of pseudonoise (PN) chips, or‘Chips Per Modulation Symbol’ (CPMS). Depending on the CPMS requirementfor a particular frame of data, the addressing can be generated bysimply selecting the appropriate range of the counter. Note that thecounter changes state at the chip rate, meaning that if we were lookingfor a CPMS of four, we would select the lowest bit of addressing tocorrespond to the third bit of the counter: Address [n:0]=counter[(n+2):2].

[0055] As described above, the present invention provides for anextremely streamlined approach to achieving both methods of interleavingas defined in the IS-2000 standard, while meeting the complexrequirement of frame puncturing in a straightforward manner. Sinceoutput addressing is directly driven by the PN index or a counter lockedto the reverse link timing, it is a simple matter of range selection toachieve all possible configurations required in the IS-2000 standard.

[0056] While the prior art requires the use of complex counters, statemachines, and terminal count parameters, to achieve the puncturing ofsub-20 ms frames. It is easily accomplished via the use of a singlecontiguous memory and interleaver engine that resides on the input sideof the interleaver memory as provided by the present invention. Theoverall structure of the approach taken in this invention affordsmaximum flexibility within a simplified architecture.

[0057] While the preferred embodiments of the invention have beenillustrated and described, it will be clear that the invention is not solimited. Numerous modifications, changes, variations, substitutions andequivalents will occur to those skilled in the art without departingfrom the spirit and scope of the present invention as defined by theappended claims.

What is claimed is:
 1. A modulator circuit, comprising: a memory forstoring interleaved data, the memory having a write address port; and aninverse interleaving address generator coupled to the write addressport.
 2. A modulator circuit as defined in claim 1, wherein the inverseinterleaving address generator provides a write address, I, to thememory equal to: I=kJ+P, where J can be defined as 3*2^(n) or 9*2^(n);P=A_(i)/2^(m) and A_(i) is the requested address; k=BROm (A_(i) mod2^(m)); and BROm(y)=bit-reversed m-LSBs of y.
 3. A modulator as definedin claim 1, wherein the inverse interleaving address generator mergesthe write and read IS-95 interleaving functions as defined in theIS-2000 standard and combines them into one function.
 4. A modulator asdefined in claim 1, wherein the inverse interleaving address generatorperforms a address mapping function that takes an original row address(A_(OR)) and transfer number (TN) and provides a new row address (A_(n))to the memory which follows the equation: If TN=0˜5, A _(n) =A_(or)*3;If TN=6˜11, A _(n) =[A _(or)*3]+1; andIf TN=12˜17, A _(n) =[A_(or)*3]+2.
 5. A modulator as defined in claim 1, wherein the modulatorcomprises a Direct Sequence Spread Spectrum (DSSS) modulator.
 6. Amodulator as defined in claim 4, wherein the interleaving addressgenerator further comprises: a multiply-by-3 circuit; a modulo-6counter; and a modulo 3 counter coupled to the modulo-6 counter and themultiply by 3 circuit.
 7. A modulator as defined in claim 1, wherein theinverse interleaving address generator provides addresses to the memorycompliant with the IS-95 and the IS-2000 interleaving standards.
 8. Amodulator as defined in claim 1, wherein the memory includes a readaddress input port, and the modulator further comprises: a rangeselector circuit having an input port for receiving a pseudonoise (PN)index or a reverse link frame timing signal and an output port forproviding a read address to the memory.
 9. A modulator as defined inclaim 1, wherein the memory includes a read address input port and themodulator further comprises: a range selector circuit having an outputport for providing a read address to the memory, and the range selectorcircuit includes a counter and the range selector circuit provides aread address [n:0]=counter [(n+2):2].
 10. A modulator as defined inclaim 1, wherein the memory includes a data input port and the modulatorfurther comprising: a channel encoder having an input port for receivingdata; and a puncturing circuit having an input port coupled to thechannel encoder output port, the puncturing circuit having an outputport coupled to the data input port of the memory.
 11. A modulator asdefined in claim 10, wherein the inverse interleaving address generatorperforms an inverse interleaving function in the case IS-2000 compliantinterleaving is required and combines the necessary writing by columnand reading by row functions in the case IS-95 compliant interleaving isrequired.
 12. A Direct Sequence Spread Spectrum (DSSS) modulator,comprising: a memory for storing interleaved data having a read addressport; and a counter having an output port coupled to the read addressport, said counter having a first input port for receiving a pseudonoise(PN) or a reverse link frame timing signal, and a second input port forreceiving a range select signal.
 13. A modulator as defined in claim 12,wherein the counter changes state at a rate equal to modulation dataduration for a particular frame of data.
 14. A modulator as defined inclaim 12, wherein depending on the Chip Per Modulation Symbol (CPMS) fora particular frame of data, the addressing of the interleaver memory isperformed by selecting a particular range select signal provided to thecounter.
 15. A method for interleaving data, comprising the steps of:providing a memory; and sending a write address, I, to the memory equalto: I=kJ+P, where J can be defined as 3*2^(n) or 9*2^(n); P=A_(i)/2^(m)and A_(i) is the requested address; k=BROm (A_(i) mod 2^(m)); andBROm(y)=bit-reversed m−LSBs of y.
 16. A method as defined in claim 15,wherein the interleaved data is compliant with the IS-2000 standard. 17.A method for interleaving data, comprising the steps of: providing amemory; and performing an address mapping function that takes anoriginal row address (A_(OR)) and transfer number (TN) and provides anew row address (A_(n)) to the memory which follows the equation: IfTN=0˜5, A _(n) =A _(or)*3;If TN=6˜11, A _(n) =[A _(or)*3]+1; andIfTN=12˜17, A _(n) =[A _(or)*3]+2.
 18. A method as defined in claim 17,wherein the interleaved data is compliant with the IS-95 standard.